1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to an SRAM and so forth, which comprises memory cells of the 8-transistor type.
2. Description of the Related Art
An achievement of low power consumption in an LSI requires a low supply voltage. The lower limit of the supply voltage in the LSI is determined by an SRAM inside the LSI in many cases due to the problem of disturbance in memory cells. Namely, in a conventional memory cell of the 6-transistor type, when a word line is selected for read operation, a precharged bit line is connected to an internal node contained in a flip-flop via a transfer transistor and the internal node is slightly pulled up. Therefore, data in the flip-flop becomes unstable and a lowered supply voltage may destruct data. As a measure against such the problem of disturbance, the use of memory cells of the 8-transistor type having a read port separated is proposed (Document 1: L. Chang, et al., Symposium on VLSI Technology 2005, p 128). The memory cell of the 8-transistor type newly includes, in addition to the memory cell of the 6-transistor type, a read bit line and a read word line, a drive transistor operative to drive the read bit line, and a transfer gate transistor operative to connect the read bit line with the drive transistor. The gate of the transfer gate transistor is controlled by the read word line and the gate of the drive transistor is connected to the internal node. In this configuration, the internal node is not connected directly to the read bit line. Accordingly, the internal node is not pulled up at the time of read, and thus the problem of disturbance can be prevented. Operation at the time of write is similar to that of the memory cell of the 6-transistor type.
The SRAM comprising such the conventional memory cell of the 8-transistor type adds two transistors for drive-use and for transfer gate-use to one node in the memory cell of the 6-transistor type. Accordingly, it is required to execute single-phase, single-ended read, in the sense of preventing the increase in the number of elements. Therefore, read operation is executed with a logic circuit such as an inverter operative to decide “H” level/“L” level on the bit line. The reading speed and accuracy can be ensured by giving a rapid full swing to the bit line. Such the fast drive of the bit line requires the number of cells connected with the bit line to be reduced to around 8-32 cells and therefore extremely lowers the cell occupation ratio as a problem.